This invention relates to semiconductor integrated circuits and more particularly to methods for producing electrically isolated devices in such circuits.
Various techniques have been utilized in integrated circuit manufacturing processes to form isolated regions on silicon wafers in which various microelectronic devices, e.g., metal oxide semiconductor (MOS) and bipolar transistors, can be formed. The primary advantages gained by providing isolated regions on silicon wafers are the reduced parasitic capacitive coupling of devices to the wafers and the excellent inter-isolation of devices formed in different regions on the wafers.
A commonly used method for manufacturing MOS transistors and bipolar transistors in integrated circuits at a major surface of a semiconductive silicon substrate involves the local oxidation of silicon (LOCOS) process for electrically isolating neighboring transistors. In that process, a major surface of a silicon substrate is masked with a silicon dioxide or silicon nitride layer having window areas and the exposed silicon in these window areas is oxidized. However, as a result of lateral oxidation of silicon under the mask, the LOCOS process undesirably increases the required distance between neighboring transistors and undesirably reduces transistor packing density.
In order to avoid the aforementioned disadvantages of the LOCOS process, selective epitaxial growth (SEG) of silicon has been proposed as an alternative. In SEG, an epitaxial layer of semiconductive monocrystalline silicon is grown on selected regions of a semiconductive silicon body. These selected regions are located at the bottom of windows formed by insulating layers which are positioned on the silicon body. At the same time, no silicon accumulates on the insulating layer, hence the use of the word xe2x80x9cselectivexe2x80x9d in SEG.
Continued efforts are directed toward the miniaturization of circuits so that more devices can be fabricated on a single chip or wafer. This applies to MOS-type circuits, such as CMOS circuits, as well as to bipolar circuits. Indeed, there exists many applications in which both MOS and bipolar circuits are utilized on the same chip.
However, MOS and bipolar circuits are commonly fabricated on a single epitaxial silicon layer which has been uniformly doped to a single, fixed dopant concentration. Thus, the number of variables which can be controlled during manufacture of both MOS and bipolar devices on a single epitaxial silicon layer is limited by the fixed concentration of dopant in the epitaxial silicon.
In accordance with the present invention, a process for forming isolated active device regions on a silicon substrate is provided. The process of the invention involves forming at least one trench in a silicon substrate to define at least two active device regions on the substrate to be electrically isolated from each other, filling the trench with an electrically insulative material, performing a masking and etching operation to expose at least one active device region on the substrate, selectively growing a first epitaxial layer of silicon on the exposed active device region, performing a masking and etching operation to expose at least one other active device region on the substrate and selectively growing a second epitaxial layer of silicon on the other exposed active device region on the substrate, the first epitaxial layer and second epitaxial layer being doped with impurity ions to the same or different doping concentrations to provide at least two isolated active device regions on the silicon substrate.
Further in accordance with the present invention, a variety of devices can be formed at the isolated active device regions on the silicon substrate to provide an integrated circuit. The active device regions can be doped doping concentrations which are specifically tailored to the devices which are subsequently formed at those regions. Thus, a primary advantage of this invention is that performance optimized devices having different doping profiles, e.g., CMOS and bipolar devices, particularly vertical bipolar devices, can be formed simultaneously and independently of each other on the same chip. The process of the invention is carried out with a minimum of operations and avoids the need to make costly modifications to manufacturing operations.
The phrase xe2x80x9cperformance optimizedxe2x80x9d as utilized herein shall be understood to refer to devices which are maximized for current and/or voltage gain.